In the manufacture of semiconductor devices, aluminum has been used almost exclusively as the main material for interconnects. However, recent developments in this field of the art have shown that copper is posed to take over as the main on-chip conductor for all types of integrated circuits. Compared to aluminum, copper has a lower resistance, namely less than 2 .mu..OMEGA.-cm, even when deposited in narrow trenches, versus more than 3 .mu..OMEGA.-cm for aluminum alloys. This lower resistance is critically important in high-performance microprocessors and fast static RAMs, since it enables signals to move faster by reducing the so-called "Resistance-Capacitance" (RC) time delay. Additionally, copper has a superior resistance to electromigration, which leads to lower manufacturing costs as compared to aluminum-based structures.
During the manufacture of semiconductor devices, a wafer undergoes a sequence of photolithography-etching steps to produce a plurality of patterned layers (stacks). Then, depending on the specific layers or production process, the uppermost layer of the wafer may or may not undergo a CMP process to provide a smooth surface of this layer.
FIG. 1 illustrates the cross section of one possible example of a stack-like wafer structure 1 having aluminums interconnects. A silicon layer 2 serves as a substrate on which the stack is produced by sequentially depositing additional layers. A first layer 4 of silicon oxide, a so-called "Interlayer Dielectric (ILD) insulating layer", is deposited on the substrate 2, and aluminum interconnects 6 are formed on the layer 4 by the deposition, photolithography and etching processes. Spaces between the interconnects 6 are filled with a further ILD layer 8. Tungsten (or other metal) vias 10 are produced above the aluminum interconnects 6 by the photolithography and deposition processes, and are aimed at connecting the lower is aluminum layer 6 (line) with an upper one 12. The aluminum layer 12 is then patterned to form the required connections. Prior to depositing the upper aluminum layer 12, a CMP process is applied to the ILD layer 8 to flatten its upper surface. Hence, the upper aluminum layer 12 is almost smooth, and the only local topography existing therein is that caused by dimples 10A in the upper surface of the tungsten 10. As indicated above, all the spaces between the metal features are filled with the Silicon Oxide ILD layer 8 or other dielectric layers.
FIG. 2 illustrates a cross section of a stack-like wafer structure 20 utilizing copper interconnects patterned with a known dual Damascene process. The structure 20 includes a silicon layer (substrate) 22 (whose provision is optional), ILD layers 23A and 23B, and a patterned Silicon Nitride (SiN) layer 24. For a self-aligned via scheme, the SiN layer 24 should be patterned to form vias later on. Thereafter, an ILD layer 26 is deposited on top of the patterned SiN layer 24. Then, patterning (i.e., photolithography) and etching processes are applied to the layer 26 to form trenches therein. During the etching procedure, the layer 26 is removed up to SiN layer 24 within regions 28, while within regions 28A etching continues up to the layer 23B to form vias 29. Those manufacturers who do not use the SiN layer 24 have to conduct a more difficult two-step etching with two photolithography steps on a single thick silicone oxide layer. Further produced is a diffusion tantalum-based barrier layer 30 (or TiN or Ti), whose provision is aimed at preventing copper migration into ILD layers 23A and 23B. Copper is deposited by one of the known techniques, such as CVD, PVD electroplating or electroless plating. If electroplating is used, a thin copper seed layer 32 should be deposited above the diffusion layer 30 as a prerequisite for electroplating. Thus, depending on the deposition process, a so-obtained uppermost copper layer 34 has certain topography.
When manufacturing the aluminum-based structure 1 (FIG. 1), the application of a CMP process to the uppermost aluminum layer 12 is usually not needed. As for the copper-based structure 20 (or tungsten-based structure as well), the manufacturing process requires the use of metal removal. This is true also for processes where aluminum is deposited by the dual Daemascene process.
Copper has properties that add to the polishing difficulties. Unlike tungsten, it is a soft metal and subject to scratching and embedding particles during polishing. Additionally, owing to the fact that copper is highly electrochemically active and does not form a natural protective oxide, it corrodes easily.
With the conventional technology of planarization, ILD polishing occurs after every metal deposition and etch step. The same is not true for damascene processing, wherein the post-polish surface is expected to be free of topography. However, topography is induced because of the erosion of densely packed small features arrays and dishing of the metal surface in large features.
Copper CMP is more complex because of the need completely to remove the tantalum or tantalum nitride barrier layers and copper without the overpolishing of any feature. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process.
The effects of residues, dishing and erosion present defects on the wafer induced by the CMP process applied thereto. Dishing and erosion may deteriorate the interconnections' quality, especially when the copper thickness is reduced. Indeed, the reduction of the copper thickness results in the increase of RC constants, resulting in the slower functioning of the integrated circuit. As indicated above, the lower resistance is critically import in high-performance microprocessors and fast static RAMs.
One of the possible solutions for minimizing the dishing and erosion consists of a tight control of the CMP process. This may, for example, be implemented by means of a compensation strategy using metal fills and dummy structures. However, this is a costly solution in terms of lost silicon for integrated circuits and added process and design complexity. It would be ideal to polish inlaid structures without the aid of such a process and design steps.
U.S. Pat. No. 5,872,633 discloses a method and apparatus for detecting the removal of thin film layers during the planarization. Although a technique presented in this patent is aimed at solving the residues related problem, it is capable of detecting an average thickness of a wafer under planarization, by eliminating information introduced by a pattern. It is thus evident that this technique does not provide precise measurements of the wafer's parameters, and cannot be used for determining the erosion and dishing conditions at all, which conditions, if any, are observed in the pattern area.